Quad D-Type Flip-Flop Specifications This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. 74LS175 datasheet, 74LS175 pdf, 74LS175 data sheet, datasheet, data sheet, pdf, Fairchild Semiconductor, Hex/Quad D-Type Flip-Flops with Clear

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